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| 1 features ? two different if receiving bandwidth versions are available (b if = 300 khz or 600 khz) ? 5 v to 20 v automotive compatible data interface ? ic condition indicator, sleep or active mode ? low power consumption due to configurable self polling with a programmable timeframe check ? high sensitivity, especially at low data rates ? data clock available for manchester- and bi-phase-coded signals ? minimal external circuitry requirements, no rf components on the pc board except matching to the receiver antenna ? sensitivity reduction possible even while receiving ? fully integrated vco ? so20 package ? supply voltage 4.5 v to 5.5 v, operating temperature range -40c to +105c ? single-ended rf input for easy adaptation to /4 antenna or printed antenna on pcb ? low-cost solution due to high integration level ? esd protection according to mil-std. 883 (4kv hbm) ? high image frequency suppression due to 1 mhz if in conjunction with a saw front- end filter. up to 40 db is thereby achievable with state-of-the-art saws. ? communication to microcontroller possible via a single, bi-directional data line ? power management (polling) is also possible by means of a separate pin via the microcontroller ? programmable digital noise suppression description the t5743 is a multi-chip pll receiver device supplied in an so20 package. it has been especially developed for the demands of rf low-cost data transmission systems with data rates from 1 kbaud to 10 kbaud in manchester or bi-phase code. the receiver is well suited to operate with atmel's pll rf transmitter u2741b. its main applications are in the areas of telemetering, security technology and keyless-entry systems. it can be used in the frequency receiving range of f 0 = 300 mhz to 450 mhz for ask or fsk data transmission. all the statements made below refer to 433.92 mhz and 315 mhz applications. system block diagram figure 1. system block diagram demod. if amp lna vco pll xto control t5743 1...5 c power amp. xto vco pll u2741b antenna antenna uhf ask/fsk remote control transmitter uhf ask/fsk remote control receiver uhf ask/fsk receiver t5743 preliminary rev. 4569a?rke?12/02
2 t5743 4569a?rke?12/02 pin configuration figure 2. pinning so20 1 2 3 4 5 6 7 8 10 9 19 18 17 16 14 15 13 12 11 20 avcc test agnd mixvcc lnagnd lna_in ic_active cdem data_clk mode xto lfgnd lf polling/_on dgnd n.c. lfvcc data dvcc sens t5743 pin description pin symbol function 1 sens sensitivity-control resistor 2 ic_active ic condition indicator low = sleep mode high = active mode 3 cdem lower cut-off frequency data filter 4 avcc analog power supply 5 test test pin, during operation at gnd 6 agnd analog ground 7 mixvcc power supply mixer 8 lnagnd high-frequency ground lna and mixer 9 lna_in rf input 10 n.c. not connected 11 lfvcc power supply vco 12 lf loop filter 13 lfgnd ground vco 14 xto crystal oscillator 3 t5743 4569a?rke?12/02 figure 3. block diagram 15 dvcc digital power supply 16 mode selecting 433.92 mhz/315 mhz low: f xt0 = 4.90625 mhz (usa) high: f xt0 = 6.76438 mhz (europe) 17 data_clk bit clock of data stream 18 dgnd digital ground 19 polling/_on selects polling or receiving mode low: receiving mode high: polling mode 20 data data output/configuration input pin description (continued) pin symbol function fsk/ask- demodulator and data filter if amp if amp 4. order lpf 3 mhz lpf 3 mhz dem_out limiter out rssi sensitivity reduction standby logic polling circuit and control logic fe clk vco xto 64 f cdem avcc sens agnd dgnd mixvcc lnagnd lna_in data polling/_on test data_clk mode lfgnd lfvcc xto lf dvcc lna ic_active data interface 4 t5743 4569a?rke?12/02 rf front-end the rf front-end of the receiver is a heterodyne configuration that converts the input signal into a 1 mhz if signal. according to figure 3, the front-end consists of an lna (low-noise amplifier), lo (local oscillator), a mixer and an rf amplifier. the lo generates the carrier frequency for the mixer via a pll synthesizer. the xto (crystal oscillator) generates the reference frequency f xto . the vco (voltage-controlled oscillator) generates the drive voltage frequency f lo for the mixer. f lo is dependent on the voltage at pin lf. f lo is divided by factor 64. the divided frequency is compared to f xto by the phase frequency detector. the current output of the phase frequency detec- tor is connected to a passive loop filter and thereby generates the control voltage v lf for the vco. by means of that configuration v lf is controlled in a way that f lo /64 is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: f xto = f lo /64. the xto is a one-pin oscillator that operates at the series resonance of the quartz crys- tal. according to figure 4, the crystal should be connected to gnd via a capacitor cl. the value of that capacitor is recommended by the crystal supplier. the value of cl should be optimized for the individual board layout to achieve the exact value of f xto and hereby of f lo . when designing the system in terms of receiving bandwidth, the accuracy of the crystal and the xto must be considered. figure 4. pll peripherals the passive loop filter connected to pin lf is designed for a loop bandwidth of bloop = 100 khz. this value for bloop exhibits the best possible noise performance of the lo. figure 4 shows the appropriate loop filter components to achieve the desired loop bandwidth. if the filter components are changed for any reason please notify that the maximum capacitive load at pin lf is limited. if the capacitive load is exceeded, a bit check may no longer be possible since f lo cannot settle in time before the bit check starts to evaluate the incoming data stream. self polling does therefore also not work in that case. f lo is determined by the rf input frequency f rf and the if frequency f if using the follow- ing formula: f lo = f rf - f if to determine f lo , the construction of the if filter must be considered at this point. the nominal if frequency is f if = 1 mhz. to achieve a good accuracy of the filter?s corner fre- quencies, the filter is tuned by the crystal frequency f xto . this means that there is a fixed relation between f if and f lo . this relation is dependent on the logic level at pin mode. dvcc xto lf lfvcc lfgnd v c c10 r1 c9 s l v s r1 = 820 c9 = 4.7 nf c10 = 1 nf 5 t5743 4569a?rke?12/02 this is described by the following formulas: the relation is designed to achiev e the nominal if frequency of f if = 1 mhz for most applications. for applications where f rf = 315 mhz, mode must be set to ?0?. in the case of f rf = 433.92 mhz, mode must be set to ?1?. for other rf frequencies, f if is not equal to 1 mhz. f if is then dependent on the logical level at pin mode and on f rf . table 1 summarizes the different conditions. the rf input either from an antenna or from a generator must be transformed to the rf input pin lna_in. the input impedance of that pin is provided in the electrical parame- ters. the parasitic board inductances and capacitances also influence the input matching. the rf receiver t5743 exhibits its highest sensitivity at the best signal-to- noise ratio in the lna. hence, noise matching is the best choice for designing the trans- formation network. a good practice when designing the network is to start with power matching. from that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. if a saw is implemented into the input network a mirror frequency suppression of p ref = 40 db can be achieved. there are saws available that exhibit a notch at f = 2 mhz. these saws work best for an intermediate frequency of f if = 1 mhz. the selectivity of the receiver is also improved by using a saw. in typical automotive appli- cations, a saw is used. figure 5 shows a typical input matching network, for f rf = 315 mhz and f rf = 433.92 mhz using a saw. figure 6 illustrates an according input matching to 50 without a saw. the input matching networks shown in figure 6 are the reference net- works for the parameters given in the electrical characteristics. table 1. calculation of lo and if frequency conditions local oscillator frequency intermediate frequency f rf = 315 mhz, mode = 0 f lo = 314 mhz f if = 1 mhz f rf = 433.92 mhz, mode = 1 f lo = 432.92 mhz f if = 1 mhz 300 mhz < f rf < 365 mhz, mode = 0 365 mhz < f rf < 450 mhz, mode = 1 mode 0 (usa) : f if f lo 314 --------- - == mode 1 (europe) : f if f lo 432.92 ----------------- - == f lo f rf 1 1 314 --------- - + ------------------- = f if f lo 314 --------- - = f lo f rf 1 1 432.92 ----------------- - + --------------------------- - = f if f lo 432.92 ----------------- - = 6 t5743 4569a?rke?12/02 figure 5. input matching network with saw filter figure 6. input matching network without saw filter please notify that for all coupling conditions (see figure 5 and figure 6), the bond wire inductivity of the lna ground is compensated. c3 forms a series resonance circuit together with the bond wire. l = 25 nh is a feed inductor to establish a dc path. its value is not critical but must be large enough not to detune the series resonance circuit. for cost reduction this inductor can be easily printed on the pcb. this configuration improves the sensitivity of the receiver by about 1 db to 2 db. in in_gnd out out_gnd case_gnd b3555 t5743 c3 22p l 25n c16 100p c17 8.2p l3 toko ll2012 f27nj 27n c2 8.2p l2 toko ll2012 f33nj 33n 1 2 3,4 7,8 5 6 8 9 rf in f rf = 433.92 mhz lnagnd lna_in in in_gnd out out_gnd case_gnd b3551 t5743 c3 47p l 25n c16 100p c17 22p l3 toko ll2012 f47nj 47n c2 10p l2 toko ll2012 f82nj 82n 1 2 3,4 7,8 5 6 8 9 rf in f rf = 315 mhz lnagnd lna_in t5743 15p 25n 100p 3.3p toko ll2012 f22nj 22n 8 9 rfin f rf = 433.92 mhz lnagnd lna_in t5743 33p 25n 100p 3.3p toko ll2012 f39nj 39n 8 9 rf in f rf = 315 mhz lnagnd lna_in 7 t5743 4569a?rke?12/02 analog signal processing if amplifier the signals coming from the rf front-end are filtered by the fully integrated 4th-order if filter. the if center frequency is f if = 1 mhz for applications where f rf = 315 mhz or f rf = 433.92 mhz is used. for other rf input frequencies refer to table 1 to determine the center frequency. the t5743 is available with two different if bandwidths. t5743p3, the version with b if = 300 khz, is well suited for ask systems where atmel?s pll transmitter u2741b is used. the receiver t5743p6 employs an if bandwidth of b if = 600 khz. both versions can be used together with the u2741b in ask and fsk mode. if used in ask applica- tions, it allows higher tolerances for the receiver and pll transmitter crystals. saw transmitters exhibit much higher transmit freqeuncy tolerances compared to pll trans- mitters. generally, it is necessary to use b if = 600 khz together with such transmitters. rssi amplifier the subsequent rssi amplifier enhances the output signal of the if amplifier before it is fed into the demodulator. the dynamic range of this amplifier is dr rssi = 60 db. if the rssi amplifier is operated within its linear range, the best s/n ratio is maintained in ask mode. if the dynamic range is exceeded by the transmitter signal, the s/n ratio is defined by the ratio of the maximum rssi output voltage and the rssi output voltage due to a disturber. the dynamic range of the rssi amplifier is exceeded if the rf input signal is about 60 db higher compared to the rf input signal at full sensitivity. in fsk mode the s/n ratio is not affected by the dynamic range of the rssi amplifier. the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sens . r sens is con- nected between pin sens and gnd or v s . the output of the comparator is fed into the digital control logic. by this means it is possible to operate the receiver at a lower sensitivity. if r sens is connected to gnd, the receiver operates at full sensitivity. if r sens is connected to v s , the receiver operates at a lower sensitivity. the reduced sen- sitivity is defined by the value of r sens , the maximum sensitivity by the signal-to-noise ratio of the lna input. the reduced sensitivity depends on the signal strength at the out- put of the rssi amplifier. since different rf input networks may exhibit slightly different values for the lna gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. this matching is illustrated in figure 6 and exhibits the best possible sensitivity. r sens can be connected to v s or gnd via a microcontroller. the receiver can be switched from full sensitivity to reduced sensit ivity or vice versa at any time. in polling mode, the receiver will not wake up if the rf input signal does not exceed the selected sensitivity. if the receiver is already active, the data stream at pin data will disappear when the input signal is lower than defined by the reduced sensitivity. instead of the data stream, the pattern according to figure 7 is issued at pin data to indicate that the receiver is still active (see also figure 34). figure 7. steady l state limited data output pattern data t data_l_max data_min t 8 t5743 4569a?rke?12/02 fsk/ask demodulator and data filter the signal coming from the rssi amplifier is converted into the raw data signal by the ask/fsk demodulator. the operating mode of the demodulator is set via the bit ask/_fsk in the opmode register. logic ?l? sets the demodulator to fsk, applying ?h? to ask mode. in ask mode, an automatic threshold control ci rcuit (atc) is used to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. this circuit effectively suppresses any kind of inband noise signals or competing transmitters. if the s/n (ratio to suppress inband noise signals) exceeds 10 db, the data signal can be detected properly. the fsk demodulator is intended to be used for an fsk deviation of 10 khz f 100 khz. in fsk mode the data signal can be detected if the s/n (ratio to suppress inband noise signals) exceeds 2 db. this value is guaranteed for all modulation schemes of a disturber signal. the output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. the data filt er improves the s/n ratio as its passband can be adopted to the characteristics of the dat a signal. the data filter consists of a 1 st -order highpass and a 2 nd -order lowpass filter. the highpass filter cut-off frequency is defined by an external capacitor connected to pin cdem. the cut-off frequency of the highpass filter is defined by the following formula: in self-polling mode, the data filter must settle very rapidly to achieve a low current con- sumption. therefore, cdem cannot be increased to very high values if self-polling is used. on the other hand, cdem must be large enough to meet the data filter require- ments according to the data signal. recommended values for cdem are given in the electrical characteristics. the cut-off frequency of the lowpass filter is defined by the selected baud-rate range (br_range). the br_range is defined in the opmode register (refer to section ?con- figuration of the receiver?). the br_range must be set in accordance to the used baud rate. the t5743 is designed to operate with data coding where the dc level of the data signal is 50%. this is valid for manchester and bi-phase coding. if other modulation schemes are used, the dc level should always remain within the range of v dc_min = 33% and v dc_max = 66%. the sensitivity may be reduced by up to 2 db in that condition. each br_range is also defined by a minimum and a maximum edge-to-edge time (t ee_sig ). these limits are defined in the electric al characteristics. they should not be exceeded to maintain full sensitivity of the receiver. receiving characteristics the rf receiver t5743 can be operated with and without a saw front-end filter. in a typical automotive application, a saw filter is used to achieve better selectivity. the selectivity with and without a saw front-end filter is illustrated in figure 8. this example relates to ask mode and the 300-khz bandwidth version of the t5743. fsk mode and the 600-khz bandwidth version of the receiver exhibits similar behavior. note that the mirror frequency is reduced by 40 db. the plots are printed relatively to the maximum sensitivity. if a saw filter is used, an insertion loss of about 4 db must be considered. fcu_df 1 2 30 k cdem ----------------------------------------------------------- = 9 t5743 4569a?rke?12/02 figure 8. receiving frequency response when designing the system in terms of receiving bandwidth, the lo deviation must be considered as it also determines the if center frequency. the total lo deviation is cal- culated to be the sum of the deviation of the crystal and the xto deviation of the t5743. low-cost crystals are specified to be within 100 ppm. the xto deviation of the t5743 is an additional deviation due to the xto circuit. this deviation is specified to be 30 ppm. if a crystal of 100 ppm is used, the total deviation is 130 ppm in that case. note that the receiving bandwidth and the if-filter bandwidth are equivalent in ask mode but not in fsk mode. polling circuit and control logic the receiver is designed to consume less than 1 ma while being sensitive to signals from a corresponding trans mitter. this is achieved via the polling circuit. this circuit enables the signal path periodically for a short time. during this time the bit-check logic verifies the presence of a valid transmitter si gnal. only if a valid signal is detected the receiver remains active and transfers the data to the connected microcontroller. if there is no valid signal present the receiver is in sleep mode most of the time resulting in low current consumption. this condition is called polling mode. a connected microcontroller is disabled during that time. all relevant parameters of the polling l ogic can be configured by the connected micro- controller. this flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. regarding the number of connection wires to the microcontroller, the receiver is very flexible. it can be either operated by a single bi-directional line to save ports to the con- nected microcontroller or it can be operated by up to five uni-directional ports. basic clock cycle of the digital circuitry the complete timing of the digital circuitry and the analog filtering is derived from one clock. according to figure 9, this clock cycle t clk is derived from the crystal oscillator (xto) in combination with a divider. the division factor is controlled by the logical state at pin mode. according to section ?rf front-end?, the frequency of the crystal oscillator (f xto ) is defined by the rf input signal (f rfin ) which also defines the operating frequency of the local oscillator (f lo ). -100.0 -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 df (mhz) dp (db) with saw without saw 10 t5743 4569a?rke?12/02 figure 9. generation of the basic clock cycle pin mode can now be set in accordance with the desired clock cycle t clk . t clk controls the following application relevant parameters: ? timing of the polling circuit including bit check ? timing of the analog and digital signal processing ? timing of the register programming ? frequency of the reset marker ? if filter center frequency (f if0 ) most applications are dominated by two transmission frequencies: f send = 315 mhz is mainly used in usa, f send = 433.92 mhz in europe. in order to ease the usage of all t clk - dependent parameters on this electrical characteristics display three conditions for each parameter. ? application usa (f xto = 4.90625 mhz, mode = l, t clk = 2.0383 s) ? application europe (f xto = 6.76438 mhz, mode = h, t clk = 2.0697 s) ? other applications (t clk is dependent on f xto and on the logical state of pin mode. the electrical characteristic is given as a function of t clk ). the clock cycle of some function blocks depends on the selected baud-rate range (br_range) which is defined in the opmode register. this clock cycle t xclk is defined by the following formulas for further reference: br_range = br_range0: t xclk = 8 t clk br_range1: t xclk = 4 t clk br_range2: t xclk = 2 t clk br_range3: t xclk = 1 t clk polling mode according to figure 10, the receiver stays in polling mode in a continuous cycle of three different modes. in sleep mode the signal processing circuitry is disabled for the time period t sleep while consuming low current of i s =i soff . during the start-up period, t startup , all signal processing circuits are enabled and settled. in the following bit-check mode, the incoming data stream is analyzed bit by bit contra a valid transmitter signal. if no valid signal is present, the receiver is set back to sleep mode after the period t bit-check . this period varies check by check as it is a statistical process. an average value for t bit-check is given in the electrical characteristics. during t startup and t bit-check the current consumption is i s =i son . the condition of the receiver is indicated on pin ic_active. the average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: dvcc xto mode t f 16 15 14 clk xto xto divider :14/:10 l : usa(:10) h: europe(:14) 11 t5743 4569a?rke?12/02 during t sleep and t startup the receiver is not sensitive to a transmitter signal. to guaran- tee the reception of a transmitted command the transmitter must start the telegram with an adequate preburst. the required length of the preburst depends on the polling parameters t sleep , t startup , t bit-check and the start-up time of a connected microcontroller (t start,c ). thus, t bit-check depends on the actual bit rate and the number of bits (n bit-check ) to be tested. the following formula indicates how to calculate the preburst length. t preburst t sleep + t startup + t bit-check + t start_c sleep mode the length of period t sleep is defined by the 5-bit word sleep of the opmode register, the extension factor xsleep (according to table 9), and the basic clock cycle t clk . it is calculated to be: t sleep = sleep x sleep 1024 t clk in us- and european applications, the maximum value of t sleep is about 60 ms if xsleep is set to 1. the time resolution is about 2 ms in that case. the sleep time can be extended to almost half a second by setting xsleep to 8. xsleep can be set to 8 by bit xsleep std to 1. according to table 8, the highest register value of sleep sets the receiver into a perma- nent sleep condition. the receiver remains in that condition until another value for sleep is programmed into the opmode register. this function is desirable where several devices share a single data line and may also be used for microcontroller polling ? via pin polling/_on, the receiver can be switched on and off. i spoll i soff t sleep i son t startup t bit-check + + t sleep t startup t bit-check ++ ------------------------------------------------------------------------------------------------------------- - = 12 t5743 4569a?rke?12/02 figure 10. polling mode flow chart sleep mode: all circuits for signal processing are disabled. only xto and polling logic is enabled. output level on pin ic_active => low i s = i soff start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active => high bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active => high receiving mode: the receiver is turned on permanently and passes the data stream to the connected mc. it can be set to sleep mode through an off command via pin data or polling/_on. output level on pin ic_active => high bit-check ok ? off command sleep: 5-bit word defined by sleep0 to sleep4 in opmode register xsleep: extension factor defined by xsleep std according to table 9 t clk : basic clock cycle defined by f xto and pin mode t startup : is defined by the selected baud rate range and tclk. the baud-rate range is defined by baud0 and baud1 in the opmode register. t bit-check : depends on the result of the bit check. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud- rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register no yes t sleep = sleep x sleep 1024 t clk i s = i son t startup i s = i son t bit-check i s = i son sleep mode: all circuits for signal processing are disabled. only xto and polling logic is enabled. output level on pin ic_active => low i s = i soff start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active => high bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active => high receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or polling/_on. output level on pin ic_active => high bit-check ok ? off command sleep: 5-bit word defined by sleep0 to sleep4 in opmode register xsleep: extension factor defined by xsleep std according to table 9 t clk : basic clock cycle defined by f xto and pin mode t startup : is defined by the selected baud rate range and t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. t bit-check : depends on the result of the bit check. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud- rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register no yes t sleep = sleep x sleep 1024 t clk i s = i son t startup i s = i son t bit-check i s = i son sleep mode: all circuits for signal processing are disabled. only xto and polling logic is enabled. output level on pin ic_active => low i s = i soff start-up mode: the signal processing circuits are enabled. after the start-up time (t startup ) all circuits are in stable condition and ready to receive. output level on pin ic_active => high bit-check mode: the incomming data stream is analyzed. if the timing indicates a valid transmitter signal, the receiver is set to receiving mode. otherwise it is set to sleep mode. output level on pin ic_active => high receiving mode: the receiver is turned on permanently and passes the data stream to the connected microcontroller. it can be set to sleep mode through an off command via pin data or polling/_on. output level on pin ic_active => high bit-check ok ? off command sleep: 5-bit word defined by sleep0 to sleep4 in opmode register xsleep: extension factor defined by xsleep std according to table 9 t clk : basic clock cycle defined by f xto and pin mode t startup : is defined by the selected baud rate range and t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register. t bit-check : depends on the result of the bit check. if the bit check is ok, t bit-check depends on the number of bits to be checked (n bit-check ) and on the utilized data rate. if the bit check fails, the average time period for that check depends on the selected baud- rate range and on t clk . the baud-rate range is defined by baud0 and baud1 in the opmode register no yes t sleep = sleep x sleep 1024 t clk i s = i son t startup i s = i son t bit-check i s = i son 13 t5743 4569a?rke?12/02 figure 11. timing diagram for complete successful bit check bit-check mode in bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. this is done by subse- quent time frame checks where the distances between two signal edges are continuously compared to a programmable time window. the maximum count of this edge-to-edge tests before the receiver switches to receiving mode is also programmable. configuring the bit check assuming a modulation scheme that contains two edges per bit, two time frame checks are verifying one bit. this is valid for manchester, bi-phase and most other modulation schemes. the maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable n bit-check in the opmode register. this implies 0, 6, 12 and 18 edge to edge checks respectively. if n bit-check is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. in the presence of a valid transmitter signal, the bit check takes less time if n bit?check is set to a lower value. in polling mode, the bit-check time is not dependent on n bit-check . figure 11 shows an example where 3 bits are tested successfully and the data signal is transferred to pin data. according to figure 12, the time window for the bit check is defined by two separate time limits. if the edge-to-edge time t ee is in between the lower bit-check limit t lim_min and the upper bit-check limit t lim_max , the check will be continued. if t ee is smaller than t lim_min or t ee exceeds t lim_max , the bit check will be terminated and the receiver switches to sleep mode. figure 12. valid time window for bit check for best noise immunity it is recommended to use a low span between t lim_min and t lim_max . this is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. a ?11111...? or a ?10101...? se quence in manchester or bi-phase is a good choice concerning that advice. a good compromise between receiver sensitivity and susceptibility to noise is a time window of 25% regarding the expected edge-to-edge time t ee . using pre-burst patterns that contain various edge-to-edge time periods, the bit-check limits must be programmed according to the required span. the bit-check limits are determined by means of the formula below. bit check ic_active data_out (data) 1/2 bit start-up mode ( number of checked bits: 3 ) bit check ok 1/2 bit 1/2 bit 1/2 bit 1/2 bit 1/2 bit receiving mode dem_out bit-check mode t start-up t bit-check dem_out t ee t lim_min t lim_max 1/f sig 14 t5743 4569a?rke?12/02 t lim_min = lim_min t xclk t lim_max = (lim_max ?1) t xclk lim_min and lim_max are defined by a 5-bit word each within the limit register. using above formulas, lim_min and lim_max can be determined according to the required t lim_min , t lim_max and t xclk . the time resolution defining t lim_min and t lim_max is t xclk . the minimum edge-to-edge time t ee (t data_l_min , t data_h_min ) is defined according to the section ?receiving mode?. the lo wer limit should be set to lim_min 10. the maximum value of the upper limit is lim_max = 63. if the calculated value for lim_min is < 19, it is recommended to check 6 or 9 bits (n bit-check ) to prevent switching to receiving mode due to noise. figure 13, figure 14 and figure 15 illustrate the bit check for the bit-check limits lim_min = 14 and lim_max = 24. when the ic is enabled, the signal processing circuits are enabled during t startup . the output of the ask/fsk demodulator (dem_out) is unde- fined during that period. when the bit check becomes active, the bit-check counter is clocked with the cycle t xclk . figure 13 shows how the bit check proceeds if the bit-check counter value cv_lim is within the limits defined by lim_min and lim_max at the occurrence of a signal edge. in figure 14 the bit check fails as the value cv_lim is lower than the limit lim_min. the bit check also fails if cv_lim reaches lim_max. this is illustrated in figure 15. figure 13. timing diagram during bit check figure 14. timing diagram for failed bit check (condition: cv_lim < lim_min) bit check ic_active dem_out bit-check- counter 0 2 345 6 245 1 7 8 1 3 6789 111213 14 10 1/2 bit 15 16 17 18 1 234 56 ( lim_min = 14, lim_max = 24 ) 7891011 12 13 14 15 1234 1/2 bit 1/2 bit bit check ok bit check ok t xclk start-up mode bit-check mode t start-up t bit-check bit check ic_active bit-check- counter 0 2345 6 245 1 1 36 789 1112 10 1/2 bit start-up mode 0 ( lim_min = 14, lim_max = 24 ) sleep mode bit check failed ( cv_lim < lim_min ) dem_out bit-check mode t start-up t bit-check t sleep 15 t5743 4569a?rke?12/02 figure 15. timing diagram for failed bit check (condition: cv_lim lim_max) duration of the bit check if no transmitter signal is present during t he bit check, the output of the ask/fsk demodulator delivers random signals. the bit check is a statistical process and t bit-check varies for each check. therefore, an average value for t bit-check is given in the electrical characteristics. t bit-check depends on the selected baud-rate range and on t clk . a higher baud-rate range causes a lower value for t bit-check resulting in a lower current consump- tion in polling mode. in the presence of a valid transmitter signal, t bit-check is dependent on the frequency of that signal, f sig , and the count of the checked bits, n bit-check . a higher value for n bit-check thereby results in a longer period for t bit-check requiring a higher value for the transmitter pre-burst t preburst . receiving mode if the bit check was successful for all bits specified by n bit-check , the receiver switches to receiving mode. according to figure 11, the internal data signal is switched to pin data in that case and the data clock is available after the start bit has been detected (figure 22). a connected microcontroller can be woken up by the negative edge at pin data or by the data clock at pin data_clk. the re ceiver stays in that condition until it is switched back to polling mode explicitly. digital signal processing the data from the ask/fsk demodulator (dem_out) is digitally processed in different ways and as a result converted into the output signal data. this processing depends on the selected baud-rate range (br_range). figure 16 illustrates how dem_out is syn- chronized by the extended clock cycle t xclk . this clock is also used for the bit-check counter. data can change its state only after t xclk has elapsed. the edge-to-edge time period t ee of the data signal as a result is always an integral multiple of t xclk . the minimum time period between two edges of the data signal is limited to t ee t data_min . this implies an efficient suppression of spikes at the data output. at the same time it limits the maximum frequency of edges at data. this eases the interrupt handling of a connected microcontroller. the maximum time period for data to stay low is limited to t data_l_max . this function is employed to ensure a finite response time in programming or switching off the receiver via pin data. t data_l_max is thereby longer than the maximum time period indicated by the transmitter data stream. figure 18 gives an example where dem_out remains low after the receiver has switched to receiving mode. bit check ic_active bit-check- counter 0 23 45 6 245 1 7 367 8 9 11 12 10 1/2 bit start-up mode 20 ( lim_min = 14, lim_max = 24 ) sleep mode bit check failed ( cv_lim >= lim_max ) 13 14 15 16 17 18 19 21 22 23 24 0 1 dem_out bit-check mode t start-up t bit-check t sleep 16 t5743 4569a?rke?12/02 figure 16. synchronization of the demodulator output figure 17. debouncing of the demodulator output figure 18. steady l state limited data output pattern after transmission after the end of a data transmission, the receiver remains active. depending on the bit noise_disable in the opmode register, the output signal at pin data is high or ran- dom noise pulses appear at pin data (see section ?digital noise supression?). the edge-to-edge time period t ee of the majority of these noise pulses is equal or slightly higher than t data_min . clock bit-check counter data_out (data) t xclk dem_out t ee data_out (data) dem_out t ee t ee t data_min t ee t data_min t data_min bit check ic_active data_out (data) start-up mode receiving mode t data_l_max t data_min bit-check mode dem_out 17 t5743 4569a?rke?12/02 switching the receiver back to sleep mode the receiver can be set back to polling mode via pin data or via pin polling/_on. when using pin data, this pin must be pulled to low for the period t1 by the connected microcontroller. figure 19 illustrates the timing of the off command (see also figure 34). the minimum value of t1 depends on br_range. the maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. note also that an internal reset for the opmode and the limit register will be generated if t1 exceeds the specified values. this item is explained in more detail in the section ?configuration of the receiver?. setting the receiver to sleep mode via data is achieved by programming bit 1 to be ?1? during the register configuration. only one sync pulse (t3) is issued. the duration of the off command is determined by the sum of t1, t2 and t10. after the off command the sleep time t sleep elapses. note that the capacitive load at pin data is limited (see section ?data interface?). figure 19. timing diagram of the off-command via pin data figure 20. timing diagram of the off-command via pin polling/_on data_out (data) serial bi-directional data line x bit 1 ("1") x t1 t2 t3 t4 t5 t7 (start bit) start-up mode off-command t sleep receiving mode t10 sleep mode t start-up ic_active out1 (mc) data_out (data) serial bi-directional data line x bit 1 ("1") x t1 t2 t3 t4 t5 t7 (start bit) start-up mode off-command t sleep receiving mode t10 sleep mode t start-up ic_active out1 (microcontroller) data_out (data) serial bi-directional data line x bit 1 ("1") x t1 t2 t3 t4 t5 t7 (start bit) start-up mode off-command t sleep receiving mode t10 sleep mode t start-up ic_active out1 (microcontroller data_out (data) serial bi-directional data line x bit 1 ("1") x t1 t2 t3 t4 t5 t7 (start bit) start-up mode off-command t sleep receiving mode t10 sleep mode t start-up ic_active out1 (microcontroller) polling/_on data_out (data) serial bi-directional data line receiving mode x sleep mode start-up mode bit-check mode receiving mode x bit check ok x x t on2 t on3 ic_active 18 t5743 4569a?rke?12/02 figure 21. activating the receiving mode via pin polling/_on figure 20 illustrates how to set the receiver back to polling mode via pin polling/_on. the pin polling/_on must be held to low for the time period t on2 . after the positive edge on pin polling/_on and the delay t on3 , the polling mode is active and the sleep time t sleep elapses. this command is faster than using pin data at the cost of an additional connection to the microcontroller. figure 21 illustrates how to set the receiver to receiving mode via the pin poll- ing/_on. the pin polling/_on must be held to low. after the delay t on1 , the receiver changes from sleep mode to start-up mode regardless the programmed values for t sleep and n bit-check . as long as polling/_on is held to low, the values for t sleep and n bit- check will be ignored, but not deleted (see also section ?digital noise suppression?). if the receiver is polled exclusively by a microcontroller, t sleep must be programmed to 31 (permanent sleep mode). in this case the receiver remains in sleep mode as long as polling/_on is held to high. data clock the pin data_clk makes a data shift clock available to sample the data stream into a shift register. using this data clock, a microcontroller can easily synchronize the data stream. this clock can only be used for manchester and bi-phase coded signals. generation of the data clock: after a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at pin data. in receiving mode, the data clock control logic (manchester/bi-phase demodulator) is active and examines the incoming data stream. this is done, like in the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. as illustrated in figure 22, only two distances between two edges in manchester and bi- phase coded signals are valid (t and 2t). the limits for t are the same as used for the bit check. they can be programmed in the limit-register (lim_min and lim_max, see table 11 and table 12). the limits for 2t are calculated as follows: lower limit of 2t: lim_min_2t = (lim_min + lim_max) - (lim_max - lim_min)/2 upper limit of 2t: lim_max_2t= (lim_min + lim_max) + (lim_max - lim_min)/2 (if the result for ?lim_min_2t? or ?lim_max_2t? is not an integer value, it will be round up.) polling/_on data_out (data) serial bi-directional data line sleep mode receiving mode x x t on1 start-up mode ic_active 19 t5743 4569a?rke?12/02 the data clock is available, after the data clock control logic has detected the distance 2t (start bit) and is issued with the delay t delay after the edge on pin data (see figure 22). if the data clock control logic detects a ti ming or logical error (manchester code viola- tion), like illustrated in figure 23 and figure 24, it stops the output of the data clock. the receiver remains in receiving mode and starts with the bit check. if the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see figure 25). it is recommended to use the function of the data clock only in conjunction with the bit check 3, 6 or 9. if the bit check is set to 0 or the receiver is set to receiving mode via the pin polling/_on, the data clock is ava ilable if the data clock control logic has detected the distance 2t (start bit). note that for bi-phase-coded signals, the data clock is issued at the end of the bit. figure 22. timing diagram of the data clock figure 23. data clock disappears because of a timing error dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' bit check ok preburst data t delay t p_data_clk t2t receiving mode, data clock control logic active bit-check mode start bit dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' timing error data ( t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim_max_2t ) t ee receiving mode, bit check active receiving mode, data clock control logic active 20 t5743 4569a?rke?12/02 figure 24. data clock disappears because of a logical error figure 25. output of the data clock after a successful bit check the delay of the data clock is calculated as follows: t delay = t delay1 + t delay2 t delay1 is the delay between the internal signals data_out and data_in. for the rising edge, t delay1 depends on the capacitive load c l at pin data and the external pull-up resistor r pup . for the falling edge, t delay1 depends additionally on the external voltage v x (see figure 26, figure 27 and figure 34). when the level of data_in is equal to the level of data_out, the data clock is issued after an additional delay t delay2 . note that the capacitive load at pin data is limited. if the maximum tolerated capacitive load at pin data is exceeded, the data clock disappears (see section ?data interface?). dem_out data_out (data) data_clk '1' '1' '1' '0' '1' '1' '?' '0' '0' '1' '0' logical error (manchester code violation) data receiving mode, bit check aktive receiving mode, data clock control logic active dem_out data_out (data) data_clk '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' bit check ok data receiving mode, bit check active receiving mode, data clock control logic active start bit 21 t5743 4569a?rke?12/02 figure 26. timing characteristic of the data clock (rising edge on pin data) figure 27. timing characteristic of the data clock (falling edge of the pin data) digital noise suppression after a data transmission, digital noise appears on the data output (see figure 28). to prevent that digital noise keeps the connected microcontroller busy, it can be sup- pressed in two different ways. automatic noise suppression (see figure 29) if the bit noise_disable (table 10) in the op mode register is set to 1 (default), the receiver changes to bit-check mode at the end of a valid data stream. the digital noise is suppressed and the level at pin data is high in that case. the receiver changes back to receiving mode, if the bit check was successful. this way to suppress the noise is recommended if the data stream is manchester or bi- phase coded and is active after power on. figure 30 illustrates the behavior of the data output at the end of a data stream. note that if the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin data. the length of the pulse depends on the selected baud-rate range. v il = 0,35 * v s v ih = 0,65 * v s v x data_clk serial bi-directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay v il = 0,35 * v s v ih = 0,65 * v s v x data_clk serial bi-directional data line t delay1 t p_data_clk data_out data_in t delay2 t delay 22 t5743 4569a?rke?12/02 figure 28. output of digital noise at the end of the data stream figure 29. automatic noise suppression figure 30. occurence of a pulse at the end of the data stream controlled noise suppression by the microcontroller (see figure 31) if the bit noise_disable (see table 10) in the opmode register is set to 0, digital noise appears at the end of a valid data stream. to suppress the noise, the pin poll- ing/_on must be set to low. the receiver remains in receiving mode. then, the off- command causes the change to the start-up mode. the programmed sleep time (see table 8) will not be executed because the level at pin polling/_on is low, but the bit check is active in that case. the off-comm and activates the bit check also if the pin polling/_on is held to low. the receiver changes back to receiving mode if the bit check was successful. to activate the polling mode at the end of the data transmission, the pin polling/_on must be set to high. this way to suppress the noise is recommended if the data stream is not manchester or bi-phase coded. data_out (data) data_clk preburst data digital noise preburst data digital noise digital noise bit check ok bit-check mode bit check ok receiving mode, bit check aktive receiving mode, bit check aktive receiving mode, data clock control logic active receiving mode, data clock control logic active data_out (data) data_clk preburst data digital noise preburst data digital noise digital noise bit check ok bit-check mode bit check ok receiving mode, bit check aktive receiving mode, bit check aktive receiving mode, data clock control logic active receiving mode, data clock control logic active data_out (data) data_clk preburst data preburst data bit check ok bit check ok bit-check mode bit-check mode bit-check mode receiving mode, data clock control logic active receiving mode, data clock control logic active dem_out data_out (data) data_clk '1' '1' '1' timing error t ee bit-check mode receiving mode, data clock control logic active data stream digital noise t pulse (t ee < t lim_min or t lim_max < t ee < t lim_min_2t or t ee > t lim _ max _ 2t ) 23 t5743 4569a?rke?12/02 figure 31. controlled noise suppression configuration of the receiver the t5743 receiver is configured via two 12-bit ram registers called opmode and limit. the registers can be programmed by means of the bidirectional data port. if the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (rm). the receiver must be reprogrammed in that case. after a power-on reset (por), the registers are set to default mode. if the receiver is operated in default mode, there is no need to program the registers. table 4 shows the structure of the registers. according to table 2 bit 1 defines if the receiver is set back to polling mode via the off-command (see section ?receiving mode?) or if it is programmed. bit 2 represents the register address. it selects the appropriate register to be programmed. to get a high programming reliability, bit15 (stop bit), at the end of the programming operation, must be set to 0. table 2. effect of bit 1 and bit 2 on programming the registers table 3. effect of bit 15 on programming the register serial bi-directional data line (data_clk) preburst data digital noise preburst data digital noise bit check ok bit check ok receiving mode polling/_on off-command receiving mode start-up mode bit-check mode sleep mode bit-check mode bit 1 bit 2 action 1 x the receiver is set back to polling mode (off command) 0 1 the opmode register is programmed 0 0 the limit register is programmed bit 15 action 0 the values will be written into the register (opmode or limit) 1 the values will not be written into the register 24 t5743 4569a?rke?12/02 table 4. effect of the configuration words within the registers table 5 to table 12 illustrate the effect of the individual configuration words. the default configuration is highlighted for each word. br_range sets the appropriate baud-rate range and simultaneously defines xlim. xlim is used to define the bit-check limits t lim_min and t lim_max as shown in table 11 and table 12. table 5. effect of the configuration word br_range table 6. effect of the configuration word n bit-check bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 off-command 1 opmode register 01 br_range n bit-check modu- lation sleep x sleep noise suppression 0 baud1 baud0 bitchk1 bitchk0 ask/_ fsk sleep4 sleep3 sleep2 sleep1 sleep0 x sleepstd noise_ disable default values of bit 3...14 00010001100 1 limit register 00 lim_min lim_max 0 lim_ min5 lim_ min4 lim_ min3 lim_ min2 lim_ min1 lim_ min0 lim_ max5 lim_ max4 lim_ max3 lim_ max2 lim_ max1 lim_max0 default values of bit 3...14 01010110100 1 br_range baud-rate range/extension factor for bit-check limits (xlim) baud1 baud0 00 br_range0 (application usa/europe: br_range0 = 1.0 kbaud to 1.8 kbaud) xlim = 8 (default) 01 br_range1 (application usa/europe: br_range1 = 1.8 kbaud to 3.2 kbaud) xlim = 4 10 br_range2 (application usa/europe: br_range2 = 3.2 kbaud to 5.6 kbaud) xlim = 2 11 br_range3 (application usa/europe: br_range3 = 5.6 kbaud to 10 kbaud) xlim = 1 n bit-check number of bits to be checked bitchk1 bitchk0 00 0 0 1 3 (default) 10 6 11 9 25 t5743 4569a?rke?12/02 table 7. effect of the configuration bit modulation table 8. effect of the configuration word sleep table 9. effect of the configuration bit xsleep table 10. effect of the configuration bit noise suppression modulation selected modulation ask/_fsk 0 fsk (default) 1 ask sleep start value for sleep counter (t sleep sleep xsleep 1024 t clk ) sleep4 sleep3 sleep2 sleep1 sleep0 00000 0 (receiver is continuously polling until a valid signal occurs) 00001 1 (t sleep 2 ms for xsleep 1 in us-/ european applications) 00010 2 00011 3 ... ... ... ... ... ... 00110 6 (usa: t sleep 12.52 ms, europe: t sleep 12.72 ms) (default) ... ... ... ... ... ... 11101 29 11110 30 11111 31 (permanent sleep mode) xsleep extension factor for sleep time (t sleep = sleep xsleep 1024 t clk ) xsleep std 0 1 (default) 18 noise suppression suppression of the digital noise at pin data noise_disable 0 noise suppression is inactive 1 noise suppression is active (default) 26 t5743 4569a?rke?12/02 table 11. effect of the configuration word lim_min note: 1. lim_min is also be used to determine the margins of the data clock control logic (see section ?data clock?). table 12. effect of the configuration word lim_max note: 1. lim_max is also be used to determine the margins of the data clock control logic (see section ?data clock?). conservation of the register information the t5743 implies an integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the ram register information. according to figure 32 , a power-on reset (por) is generated if the supply voltage v s drops below the threshold voltage v threset . the default parameters are programmed into the configuration registers in that condition. once v s exceeds v threset the por is can- celled after the minimum reset period t rst . a por is also generated when the supply voltage of the receiver is turned on. to indicate that condition, the receiver displays a reset marker (rm) at pin data after a reset. the rm is represented by the fixed frequency f rm at a 50% duty-cycle. rm can be cancelled via a low pulse t1 at pin data. lim_min (1) (lim_min < 10 is not applicable) lower limit value for bit check lim_min5 lim_min4 lim_min3 lim_min2 lim_min1 lim_min0 (t lim_min = lim_min lim t clk ) 001010 10 001011 11 001100 12 ... ... ... ... ... ... 010101 21 (default) usa: t lim_min = 342 s, europe: t lim_min = 348 s) ... ... ... ... ... ... 111101 61 111110 62 111111 63 lim_max (1) (lim_max < 12 is not applicable) upper limit value for bit check lim_max5 lim_max4 lim_max3 lim_max2 lim_max1 lim_max0 (t lim_max = (lim_max - 1) xlim t clk ) 001100 12 001101 13 001110 14 ... ... ... ... ... ... 101001 41 (default) usa: t lim_max = 652 s, europe: t lim_max = 662 s) ... ... ... ... ... ... 111101 61 111110 62 111111 63 27 t5743 4569a?rke?12/02 the rm implies the following characteristics: ?f rm is lower than the lowest feasible frequency of a data signal. by this means, rm cannot be misinterpreted by the connected microcontroller. ? if the receiver is set back to polling mode via pin data, rm cannot be cancelled by accident if t1 is applied according to the proposal in the section ?programming the configuration registers?. by means of that mechanism the receiver cannot lose its register information without communicating that condition via the reset marker rm. figure 32. generation of the power-on reset programming the configuration register figure 33. timing of the register programming v s por data_out (data) 1 / f rm t rst v threset x out1 (c) data_out (data) serial bi-directional data line x bit 1 ("0") bit 2 ("1") bit 14 ("0") bit 15 ("0") x t1 t2 t3 t4 t5 t6 t8 t7 programming frame (start bit) (register- select) (poll8) (stop bit) receiving mode start-up mode t9 ic_active t sleep t start-up sleep mode 28 t5743 4569a?rke?12/02 figure 34. data interface the configuration registers are programmed serially via the bi-directional data line according to figure 33 and figure 34. to start programming, the serial data line data is pulled to low for the time period t1 by the microcontroller. when data has been released, the receiver becomes the master device. when the programming delay period t2 has elapsed, it emits 15 subsequent synchronization pulses with the pulse length t3. after each of these pulses, a program- ming window occurs. the delay until the program window starts is determined by t4, the duration is defined by t5. within the programming window, the individual bits are set. if the microcontroller pulls down pin data for the time period t7 during t5, the according bit is set to ?0?. if no programming pulse t7 is issued, this bit is set to ?1?. all 15 bits are subsequently programmed this way. the time frame to program a bit is defined by t6. bit 15 is followed by the equivalent time window t9. during this window, the equivalence acknowledge pulse t8 (e_ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. e_ack should be used to verify that the mode word was correctly transferred to the register. the register must be pro- grammed twice in that case. programming of a register is possible both in sleep- and in active-mode of the receiver. during programming, the lna, lo, lowpass filter if-amplifier and the fsk/ask manchester demodulator are disabled. the programming start pulse t1 initiates the programming of the configuration registers. if bit 1 is set to ?1?, it represents the off-command to set the receiver back to polling mode at the same time. for the length of the programming start pulse t1, the following convention should be considered: ? t1(min) < t1 < 5632 t clk : t1(min) is the minimum specified value for the relevant br_range programming respectively off-command is initiated if the receiver is not in reset mode.if the receiver is in reset mode, programming respectively off-command is not ini- tiated and the reset marker rm is still present at pin data. this period is generally used to switch the receiver to polling mode or to start the pro- gramming of a register. in reset condition, rm is not cancelled by accident. ? t1 > 7936 t clk data_in data_out input - interface data 0 ... 20 v 0 v / 5 v v x = 5 v to 20 v r pup c l v s = 4.5 v to 5.5 v i/o serial bi-directional data line t5743 microcontroller out1 m?crocontroller i d data_in data_out input - interface data 0 ... 20 v 0 v / 5 v v x = 5 v to 20 v r pup c l v s = 4.5 v to 5.5 v i/o serial bi-directional data line t5743 microcontroller out1 m?crocontroller i d 29 t5743 4569a?rke?12/02 programming respectively off-command is initiated in any case. the registers opmode and limit are set to the default values. rm is cancelled if present. this period is used if the connected micr ocontroller detected rm. if the receiver oper- ates in default mode, this time period for t1 can generally be used. note that the capacitive load at pin data is limited. data interface the data interface (see figure 34) is designed for automotive requirements. it can be connected via the pull-up resistor r pup up to 20 v and is short-circuit-protected. the applicable pull-up resistor r pup depends on the load capacity c l at pin data and the selected br_range (see table 13). more detailed information about the calculation of the maximum load capacity at pin data is given in the ?application hints u3743bm?. table 13. applicable r pup figure 35. application circuit: f rf = 433.92 mhz without saw filter br_range applicable r pup c l 1 nf b0 1.6 k to 47 k b1 1.6 k to 22 k b2 1.6 k to 12 k b3 1.6 k to 5.6 k c l 100 pf b0 1.6 k to 470 k b1 1.6 k to 220 k b2 1.6 k to 120 k b3 1.6 k to 56 k c7 2.2u 10% c6 10n 10% vs r3 >= 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test 5 agnd 6 mixvcc 7 lnagnd 8 lna_in 9 nc 10 lfvcc 11 lf 12 lfgnd 13 xto 14 dvcc 15 mode 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% c3 15p 5% q1 6.7643mhz c11 12p 2% data_clk c8 150p 10% c12 10n 10% c15 150p 10% r1 820 5% c9 4.7n 5% c10 1n 5% c16 100p 5% l2 toko ll2012 f22nj 22n 5% c17 3.3p 5% coax np0 np0 np0 np0 sensitivity reduction v x = 5 v to 20 v ic_active t5743 30 t5743 4569a?rke?12/02 figure 36. application circuit: f rf = 315 mhz without saw filter figure 37. application circuit: f rf = 433.92 mhz with saw filter c7 2.2u 10% c6 10n 10% vs r3 >= 1.6k data polling/_on r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test 5 agnd 6 mixvcc 7 lnagnd 8 lna_in 9 nc 10 lfvcc 11 lf 12 lfgnd 13 xto 14 dvcc 15 mode 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% c3 33p 5% q1 4.906mhz c11 15p 2% data_clk c8 150p 10% c12 10n 10% c15 150p 10% r1 820 5% c9 4.7n 5% c10 1n 5% c16 100p 5% l2 toko ll2012 f39nj 39n 5% c17 3.3p 5% coax np0 np0 np0 np0 sensitivity reduction v x = 5 v to 20 v ic_active t5743 t5743 c7 2.2u 10% c6 10n 10% vs r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test 5 agnd 6 mixvcc 7 lnagnd 8 lna_in 9 nc 10 lfvcc 11 lf 12 lfgnd 13 xto 14 dvcc 15 mode 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% c3 22p 5% c11 12p 2% q1 6.7643mhz c8 150p 10% c12 10n 10% c15 150p 10% c16 100p 5% c17 8,2p 5% l3 toko ll2012 f27 nj 27n 5% r1 820 5% c9 4.7n 5% c10 1n 5% in 1 in_gnd 2 case_gnd 3 4 out 5 out_gnd 6 case_gnd 7 8 b3555 coax c2 8.2p 5% l2 toko ll2012 f33nj 33n 5% np0 np0 np0 np0 np0 r3 >= 1.6k data polling/_on data_clk sensitivity reduction v x = 5 v to 20 v ic_active 31 t5743 4569a?rke?12/02 figure 38. application circuit: f rf = 315 mhz with saw filter c7 2.2u 10% c6 10n 10% vs r2 56k to 150k sens 1 ic_active 2 cdem 3 avcc 4 test 5 agnd 6 mixvcc 7 lnagnd 8 lna_in 9 nc 10 lfvcc 11 lf 12 lfgnd 13 xto 14 dvcc 15 mode 16 data_clk 17 dgnd 18 polling/_on 19 data 20 c14 33n 5% gnd c13 10n 10% c3 47p 5% c11 15p 2% q1 4.906mhz c8 150p 10% c12 10n 10% c15 150p 10% c16 100p 5% c17 22p 5% l3 toko ll2012 f47nj 47n 5% r1 820 5% c9 4.7n 5% c10 1n 5% in 1 in_gnd 2 case_gnd 3 4 out 5 out_gnd 6 case_gnd 7 8 b3551 coax c2 10p 5% l2 toko ll2012 f82nj 82n 5% np0 np0 np0 np0 np0 r3 >= 1.6k data polling/_on data_clk sensitivity reduction v x = 5 v to 20 v ic_active t5743 absolute maximum ratings parameters symbol min. max. unit supply voltage v s 6v power dissipation p tot 1000 mw junction temperature t j 150 c storage temperature t stg -55 +125 c ambient temperature t amb -40 +105 c maximum input level, input matched to 50 p in_max 10 dbm thermal resistance parameters symbol value unit junction ambient r thja 100 k/w 32 t5743 4569a?rke?12/02 electrical characteristics all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol 6.76438 mhz osc. (mode: 1) 4.90625 mhz osc. (mode: 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. basic clock cycle of the digital circuitry basic clock cycle mode = 0 (usa) mode = 1 (europe) t clk 2.0697 2.0697 2.0383 2.0383 1/f xto /10 1/f xto /14 1/f xto /10 1/f xto /14 s s extended basic clock cycle br_range0 br_range1 br_range2 br_range3 t xclk 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s polling mode sleep time (see figure 10, figure 19, and figure 33) sleep and xsleep are defined in the opmode register t sleep sleep x sleep 1024 2.0697 sleep x sleep 1024 2.0697 sleep x sleep 1024 2.0383 sleep x sleep 1024 2.0383 sleep x sleep 1024 t clk sleep x sleep 1024 t clk ms start-up time (see figure 10, and figure 11) br_range0 br_range1 br_range2 br_range3 t startup 1855 1061 1061 663 1855 1061 1061 663 1827 1045 1045 653 1827 1045 1045 653 896.5 512.5 512.5 320.5 t clk 896.5 512.5 512.5 320.5 t clk s s s s time for bit check (see figure 10) average bit-check time while polling, no rf applied (see figure 14, and figure 15) br_range0 br_range1 br_range2 br_range3 t bit-check 0.45 0.24 0.14 0.08 0.45 0.24 0.14 0.08 ms ms ms ms bit-check time for a valid input signal f sig , (see figure 11) n bit-check = 0 n bit-check = 3 n bit-check = 6 n bit-check = 9 t bit-check 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 3/f sig 6/f sig 9/f sig 3.5/f sig 6.5/f sig 9.5/f sig 1 x t xclk 3/f sig 6/f sig 9/f sig 1 t clk 3.5/f sig 6.5/f sig 9.5/f sig ms ms ms ms receiving mode intermediate frequency mode = 0 (usa) mode = 1 (europe) f if 1.0 1.0 f xto 64/314 f xto 64/432.92 mhz mhz baud-rate range br_range0 br_range1 br_range2 br_range3 br_range 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 1.8 3.2 5.6 10.0 br_range0 2 s/t clk br_range1 2 s/t clk br_range2 2 s/t clk br_range3 2 s/t clk kbaud kbaud kbaud kbaud minimum time period between edges at pin data (see figure 7, figure 17 and figure 18, with the exception of parameter t pulse ) br_range = br_range0 br_range1 br_range2 br_range3 t data-min 165 83 41.4 20.7 165 83 41.4 20.7 163 81 40.7 20.4 163 81 40.7 20.4 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk 10 t xclk s s s s 33 t5743 4569a?rke?12/02 maximum low period at pin data (see figure 7 and figure 18) br_range = br_range0 br_range1 br_range2 br_range3 t data_l_max 2152 1076 538 270 2152 1076 538 270 2120 1060 530 265 2120 1060 530 265 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk 130 t xclk s s s s delay to activate the start-up mode (see figure 21) ton1 19.7 21.8 19.4 21.5 9.5 t clk 10.5 t clk s off- command at pin polling/_on (see figure 20) ton2 16.6 16.4 8 t clk s delay to activate the sleep mode (see figure 20) ton3 17.6 19.7 17.4 19.4 8.5 t clk 9.5 t clk s pulse on pin data at the end of a data stream (see figure 30) br_range = br_range0 br_range1 br_range2 br_range3 t pulse 16.6 8.3 4.1 2.1 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 16.3 8.2 4.1 2.0 8 t clk 4 t clk 2 t clk 1 t clk 8 t clk 4 t clk 2 t clk 1 t clk s s s s configuration of the receiver frequency of the reset marker (see figure 31) f rm 117.9 117.9 119.8 119.8 hz programming start pulse (see figure 19 and figure 33) br_range = br_range0 br_range1 br_range2 br_range3 after por t1 3367 2277 1735 1464 16.43 11650 11650 11650 11650 3311 2243 1709 1442 16.18 11470 11470 11470 11470 1624 t clk 1100 t clk 838 t clk 707 t clk 7936 t clk 5632 t clk 5632 t clk 5632 t clk 5632 t clk s s s s s programming delay period (see figure 19 and figure 33) t2 795 798 783 786 384.5 t clk 385.5 t clk s synchroni- zation pulse t3 265 265 261 261 128 t clk 128 t clk s delay until of the program window starts t4 131 131 129 129 63.5 t clk 63.5 t clk s programming window t5 530 530 522 522 256 t clk 256 t clk s time frame of a bit (see figure 33) t6 1060 1060 1044 1044 512 t clk 512 t clk s programming pulse (see figure 19 and figure 33) t7 132 529 130 521 64 t clk 256 t clk s electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol 6.76438 mhz osc. (mode: 1) 4.90625 mhz osc. (mode: 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. 1 4096 t clk ------------------------------ - 1 4096 t clk ------------------------------ - 34 t5743 4569a?rke?12/02 equivalent acknowledge pulse: e_ack (see figure 33) t8 265 265 261 261 128 t clk 128 t clk s equivalent time window (see figure 33) t9 534 534 526 526 258 t clk 258 t clk s off-bit programming window (see figure 19) t10 930 930 916 916 449.5 t clk 449.5 t clk s data clock minimum delay time between edge at data and data_clk (see figure 26 and figure 27) br_range = br_range0 br_range1 br_range2 br_range3 t delay2 0 0 0 0 16.6 8.3 4.15 2.07 0 0 0 0 16.3 8.2 4.08 2.04 0 0 0 0 1 t xclk 1 t xclk 1 t xclk 1 t xclk s s s s pulswidth of negative pulse at pin data_clk (see figure 26 and figure 27) br_range = br_range0 br_range1 br_range2 br_range3 t p_data_clk 66.2 33.1 16.56 8.3 66.2 33.1 16.56 8.3 65.2 32.6 16.3 8.2 65.2 32.6 16.3 8.2 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk 4 t xclk s s s s electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameter test conditions symbol 6.76438 mhz osc. (mode: 1) 4.90625 mhz osc. (mode: 0) variable oscillator unit min. typ. max. min. typ. max. min. typ. max. electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit current consumption sleep mode (xto and polling logic active) is off 170 276 a ic active (start-up-, bit check-, receiving mode) pin data = h fsk ask is on 7.5 7.1 9.1 8.7 ma ma lna mixer (input matched according to figure 6) third-order intercept point lna/mixer/if amplifier iip3 -28 dbm lo spurious emission at rf in required according to i-ets 300220 is lorf -73 -57 dbm noise figure lna and mixer (dsb) nf 7 db lna_in input impedance at 433.92 mhz at 315 mhz zi lna_in 1.0 || 1.56 1.3 || 1.0 k || pf k || pf 1 db compression point (lna, mixer, if amplifier) referred to rf in ip 1db -40 dbm 35 t5743 4569a?rke?12/02 maximum input level ber 10 -3 , fsk mode ask mode p in_max -22 -20 dbm dbm local oscillator operating frequency range vco f vco 299 449 mhz phase noise vco/lo f osc = 432.92 mhz at 1 mhz at 10 mhz l (fm) -93 -113 -90 -110 dbc/hz dbc/hz spurious of the vco at f xto -55 -47 dbc vco gain k vco 190 mhz/v loop bandwidth of the pll for best lo noise (design parameter) r1 = 820 c9 = 4.7 nf c10 = 1 nf b loop 100 khz capacitive load at pin lf the capacitive load at pin lf is limited if bit check is used. the limitation therefore also applies to self polling. c lf_tot 10 nf xto operating frequency xto crystal frequency, appropriate load capacitance must be connected to xtal f xtal = 6.764375 mhz (eu) f xtal = 4.90625 mhz (us) f xto -30 ppm f xtal +30 ppm mhz series resonance resistor of the crystal f xto = 6.764 mhz, f xto = 4.906 mhz r s 150 220 static capacitance at pin xto to gnd c 0 6.5 pf analog signal processing input sensitivity ask 300 khz if-filter input matched according to figure 6 ask (level of carrier) ber 10 -3 , bw = 300 khz f in = 433.92 mhz/315 mhz v s = 5 v, t amb = 25 c, f if = 1 mhz br_range0 br_range1 br_range2 br_range3 p ref_ask -109 -107 -106 -104 -111 -109 -108 -106 -113 -111 -110 -108 dbm dbm dbm dbm electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit 36 t5743 4569a?rke?12/02 input sensitivity ask 600 khz if-filter input matched according to figure 6 ask (level of carrier) ber 10 -3 , bw = 600khz f in = 433.92 mhz/315 mhz v s = 5 v, t amb = 25 c, f if = 1 mhz br_range0 br_range1 br_range2 br_range3 p ref_ask -108 -106.5 -106 -104 -110 -108.5 -108 -106 -112 -110.5 -110 -108 dbm dbm dbm dbm sensitivity variation ask for the full operating range compared to t amb =25 c, v s =5v 300 khz and 600 khz version f in = 433.92 mhz/315 mhz f if = 1 mhz, p ask = p ref_ask + p ref p ref +2.5 -1.5 db sensitivity variation ask for full operating range including if-filter compared to t amb =25 c, v s = 5 v, 300 khz version f in = 433.92 mhz/315 mhz f if = 0.89 mhz to 1.11 mhz f if = 0.86 mhz to 1.14 mhz p ask = p ref_ask + p ref p ref +5.5 +7.5 -1.5 -1.5 db db 600 khz version f in = 433.92 mhz/315 mhz f if = 0.79 mhz to 1.21 mhz f if = 0.73 mhz to 1.27 mhz p ask = p ref_ask + p ref p ref +5.5 +7.5 -1.5 -1.5 db db input sensitivity fsk 300 khz if-filter input matched according to figure 6 ber 10 -3 , bw = 300 khz f in = 433.92 mhz/315 mhz v s = 5 v, t amb = 25 c f if = 1 mhz br_range0 df = 16 khz df = 10 khz to 30 khz p ref_fsk -101 -99 -104 -105.5 -105.5 dbm dbm br_range1 df = 16 khz df = 10 khz to 30 khz p ref_fsk -99 -97 -102 -103.5 -103.5 dbm dbm br_range2 df = 16 khz df = 10 khz to 30 khz p ref_fsk -97.5 -95.5 -100.5 -102 -102 dbm dbm br_range3 df = 16 khz df = 10 khz to 30 khz p ref_fsk -95.5 -93.5 -98.5 -100 -100 dbm dbm electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit 37 t5743 4569a?rke?12/02 input sensitivity fsk 600 khz if-filter input matched according to figure 6 ber 10 -3 , bw = 600 khz f in = 433.92 mhz/315 mhz v s = 5 v, t amb = 25 c f if = 1 mhz br_range0 df = 16 khz df = 10 khz to 100 khz p ref_fsk -101 -99 -104 -105.5 -105.5 dbm dbm br_range1 df = 16 khz df = 10 khz to 100 khz p ref_fsk -99 -97 -102 -103.5 -103.5 dbm dbm br_range2 df = 16 khz df = 10 khz to 100 khz p ref_fsk -97.5 -95.5 -100.5 -102 -102 dbm dbm br_range3 df = 16 khz df = 10 khz to 100 khz p ref_fsk -95.5 -93.5 -98.5 -100 -100 dbm dbm sensitivity variation fsk for the full operating range compared to t amb =25 c, v s = 5 v 300 khz and 600 khz version f in = 433.92 mhz/315 mhz f if = 1 mhz p fsk = p ref_fsk + p ref p ref +3 -1.5 db sensitivity variation fsk for the full operating range including if-filter compared to t amb = 25 c, v s = 5 v 300 khz version f in = 433.92 mhz/ 315 mhz f if = 0.89 mhz to 1.11 mhz f if = 0.86 mhz to 1.14 mhz f if = 0.82 mhz to 1.18 mhz p fsk = p ref_fsk + p ref p ref +6 +8 +11 -2 -2 -2 db db db 600 khz version f in = 433.92 mhz/ 315 mhz f if = 0.85 mhz to 1.15 mhz f if = 0.80 mhz to 1.20 mhz f if = 0.74 mhz to 1.26 mhz p fsk = p ref_fsk + p ref p ref +6 +8 +11 -2 -2 -2 db db db s/n ratio to suppress inband noise signals. noise signals may have any modulation scheme ask mode fsk mode snr ask snr fsk 12 3 db db dynamic range rssi ampl. dr rssi 60 db lower cut-off frequency of the data filter cdem = 33 nf f cu_df 0.11 0.16 0.20 khz recommended cdem for best performance br_range0 (default) br_range1 br_range2 br_range3 cdem 39 22 12 8.2 nf nf nf nf electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit f cu_df 1 2 30 k cdem ----------------------------------------------------------- = 38 t5743 4569a?rke?12/02 edge-to-edge time period of the input data signal for full sensitivity br_range0 (default) br_range1 br_range2 br_range3 t ee_sig 270 156 89 50 1000 560 320 180 s s s s upper cut-off frequency data filter upper cut-off frequency programmable in 4 ranges via a serial mode word br_range0 (default) br_range1 br_range2 br_range3 f u 2.8 4.8 8.0 15.0 3.4 6.0 10.0 19.0 4.0 7.2 12.0 23.0 khz khz khz khz reduced sensitivity r sense connected from pin sens to v s , input matched according to figure 6 dbm (peak level) r sense = 56 k , f in = 433.92 mhz, at bw = 300 khz at bw = 600 khz p ref_red -71 -67 -76 -72 -81 -77 dbm dbm r sense = 100 k , f in =433.92mhz, at bw = 300 khz at bw = 600 khz -80 -76 -85 -81 -90 -86 dbm dbm r sense = 56 k , f in = 315 mhz, at bw = 300 khz at bw = 600 khz -72 -68 -77 -73 -82 -78 dbm dbm r sense = 100 k , f in =315mhz, at bw = 300 khz at bw = 600 khz -81 -77 -86 -82 -91 -87 dbm dbm reduced sensitivity variation over full operating range r sense = 56 k r sense = 100 k p red = p ref_red + p red p red 5 6 0 0 0 0 db db reduced sensitivity variation for different values of r sense values relative to r sense = 56 k r sense = 56 k r sense = 68 k r sense = 82 k r sense = 100 k r sense = 120 k r sense = 150 k p red = p ref_red + p red p red p red p red p red p red p red 0 -3.5 -6.0 -9.0 -11.0 -13.5 db db db db db db threshold voltage for reset v threset 1.95 2.8 3.75 v electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit 39 t5743 4569a?rke?12/02 digital ports data output - saturation voltage low - max voltage at pin data - quiescent current - short-circuit current - ambient temperature in case of permanent short-circuit data input - input voltage low - input voltage high i ol 12 ma i ol = 2 ma v oh = 20 v v ol = 0.8 v to 20 v v oh = 0 v to 20 v v ol v ol v oh i qu i ol_lim t amb_sc v il v ich 13 0.65 v s 0.35 0.08 30 0.8 0.3 20 20 45 85 0.35 v s v v v a ma c v v data_clk output - saturation voltage low - saturation voltage high idata_clk = 1 ma idata_clk = -1 ma v ol v oh v s -0.4 v 0.1 v s -0.15 v 0.4 v v ic_active output - saturation voltage low - saturation voltage high iic_active = 1 ma iic_active = -1 ma v ol v oh v s -0.4 v 0.1 v s -0.15 v 0.4 v v polling/_on input - low level input voltage - high level input voltage receiving mode polling mode v il v ih 0.8 v s 0.2 v s v v mode input - low level input voltage - high level input voltage division factor = 10 division factor = 14 v il v ih 0.8 v s 0.2 v s v v test input - low level input voltage test input must always be set to low v il 0.2 v s v electrical characteristics (continued) all parameters refer to gnd, t amb = -40 c to +105 c, v s = 4.5 v to 5.5 v, f 0 = 433.92 mhz and f 0 = 315 mhz, unless otherwise specified. (for typical values: v s = 5 v, t amb = 25 c) parameters test conditions symbol min. typ. max. unit 40 t5743 4569a?rke?12/02 package information ordering information extended type number package remarks T5743P3-TG so20 tube, if bandwidth of 300 khz T5743P3-TGq so20 taped and reeled, if bandwidth of 300 khz t5743p6-tg so20 tube, if bandwidth of 600 khz t5743p6-tgq so20 taped and reeled, if bandwidth of 600 khz technical drawings according to din specifications package so20 dimensions in mm 9.15 8.65 11.43 12.95 12.70 2.35 0.25 0.10 0.4 1.27 7.5 7.3 0.25 10.50 10.20 20 11 110 printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change de vices or specifications detail ed herein at any time without n otice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of at mel are granted by the company in connection with the sale of atmel products, ex pressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4569a?rke?12/02 xm atmel ? is the registered trademark of atmel. other terms and product names may be the trademarks of others. |
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